TSN end node on RISC-V with 1000BASE-T1

Beschreibung

Demonstrate that time synchronization according to IEEE 802.1AS can be implemented successfully on Lattice’s FPGA products with RISC-V core and 1000BASE-T1 Ethernet. InES-gPTP2020, ZHAW’s implementation of IEEE 802.1AS-2020, will be ported and integrated to the RISC-V core for this purpose.
Explore the performance (latency and jitter) of one-way RGMII-to-RGMII communication for a 1000BASE-T1 link to make statements on the suitability and limitations of 1000BASE-T1 for fast distributed closed-loop implementations.

Projektleitung

Dr. Martin Ostertag

Projektteam

Projektpartner

Lattice Semiconductor Corporation

Projektstatus

laufend, gestartet 01/2026

Institut/Zentrum

Institute of Embedded Systems (InES)

Drittmittelgeber

Dritte