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Reconfigurable Heterogeneous Highly Parallel Processing Platform for safe and secure AI (REBECCA)

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REBECCA, a heavily SME-driven project, will democratize the development of novel edge AI systems. Towards this aim, REBECCA will develop a purely European complete Hardware(HW) and Software(SW) stack around a RISC-V CPU, which will provide significantly higher levels of a) performance (e.g., inferences per second), b) energy/power efficiency (e.g., inferences per joule/ watt), c) safety and d) security than the existing ones. This will be achieved by utilizing state-of-the-art technologies and by making significant scientific and technological advances in several key relevant domains, including a) processing units, b) hardware accelerators, c) reconfigurable hardware, d) tightly coupled interconnected chiplets e) HW/SW co-design and co-development tools, f) system software, g) middleware, and h) AI libraries and frameworks.

REBECCA will significantly contribute to realizing business and societal opportunities by validating and demonstrating its approach on 4 real-world use cases and 2 benchmarks based on real-world applications from the Smart appliances, Energy Generation, Infrastructure Inspection, Avionics Automotive and Health domains. In terms of HW, REBECCA will develop a novel chip consisting of two tightly coupled chiplets which will incorporate: a) RISC-V multicore, b) Neuromorphic AI Accelerator, c) Programmable array AI Accelerator, d) AI Accelerator utilizing a hierarchical processing architecture, e) DNN Accelerator, f) Reconfigurable hardware, g) Near Memory Processing, h) Memory Encryption. In terms of SW, REBECCA will implement optimized system SW, middleware, and AI libraries that will take full advantage of the underlying novel HW.

The REBECCA platform will be complemented by a novel HW/SW Design Space Exploration tool which will allow the development of highly efficient REBECCA based systems.REBECCA will additionally provide the means for safety and security modeling and verification for the developed HW and SW from the very early design stages.