Precise time stamping of messages is required in order to achieve sub microsecond accuracy with IEEE 1588 / PTP. The VHDL code for a timestamping unit and clock in combination with the necessary hardware enables such precise timestamping. The VHDL code has to be ported to the desired chip.
- Adjustable clock
- Precise time stamping at the MII
- A PPS output enables verification of synchronisation
- Code’s written in VHDL
The clock is basically a counter that increments with the frequency of the oscillator that drives the FPGA. That means e.g. if the oscillator frequency is 50 MHz the counter is incremented every 20 ns. Furthermore, drift compensation and two different ways of offset correction are implemented. The drift compensation function adjusts the counter’s value periodically (e.g. needed if oscillator constantly runs too fast/slow). The offset correction is done either by setting the desired value for the counter at once (hard) or by slowly correcting it (over a certain period of time) until the offset is fully compensated (soft).
In order to achieve time stamp precision in the nanosecond range the time stamps are generated at the MII. This enables PTP nodes to synchronize with sub microsecond accuracy.
- Full hardware support for IEEE 1588-PTP slave and master
- Synchronisation accuracy <100 ns
- 10/100 Mbit Ethernet
- 32 bit/33 MHz PCI interface
- On board FPGA is programmable via the PCI bus
- The hardware clock provides PTP time, i.e. seconds and nanoseconds. Furthermore, it is adjustable through drift- and offset compensation mechanisms.
- The Timestamping Unit takes timestamps at the MII
- Clock and timestamp resolution is one nanosecond
- Clock and timestamp quantization is 20 ns
- Pulse per second (PPS) output (5V TTL)
- Four general purpose outputs (5V TTL)
- Three general purpose inputs (5V TTL)
- Four general purpose LEDs
The IEEE 1588 enabled network interface card acts like a normal PCI network card. Supported operating systems are Linux and Windows XP. But the main feature is that it is capable of taking high precision, high resolution timestamps at the MII (media independent interface) between the PHY chip and the MAC controller. The card supports PTP version 1 and PTP version 2.
A PPS output enables developers to verify synchronization precision. The board also provides three general purpose outputs and four inputs e.g. to trigger other devices or to take time stamps of external events respectively. Since the FPGA can be programmed via the PCI bus, it is possible to extend and update the board’s functionality without dismounting the card or connecting any special hardware to it. Therefore the IEEE 1588 PCI NIC is also a highly flexible development board which can be used for various applications different from IEEE 1588.
The ECI-1588 (IEEE 1588 Ethernet Cable Interceptor) brings PTPv1 and 2 functionality to every USB2 enabled device. This enables highly precise clock synchronisation within the 100 nanosecond range without having to modify the hardware of the host system.
The ECI-1588 is a small device intercepting a computer’s 10/100 Base-TX network connection. It detects PTP frames, generates corresponding timestamps and maintains the IEEE 1588 clock. The PTP protocol software running on this computer talks via USB to the ECI to access timestamps and the clock. This flexible solution is compatible with any 10/100 Base-TX interface and does not require any hardware nor driver modifications.
- master and slave capability
- full PTPv1 and 2 protocol support
- PTP software for Windows and Linux
- no special network driver required
- IEEE 1588 hardware assistance in FPGA, upgradeable in the field
- 20 ns timestamp quantization
- Pulse Per Second (PPS) Output
- programmable trigger output
- input to timestamp external events
- LED status indicators