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HSR Core

ZHAW offers an implementation of the High-availability Seamless Redundancy Protocol (HSR according to IEC 62439-3 / 2012) as a VHDL IP core.


The ZHAW HSR core is an IP to implement an HSR Redundancy Box (RedBox) on a FPGA. It is designed to be ported easily to different platforms.


Modes of operation

A variant of the HSR Core supports IEEE 1588 (i.e. PTP)


The delivery consists of:

In order to run the reference implementation a suitable hardware kit is available. The board is delivered as a ready to run HSR RedBox. It is equipped with a Cyclone III FPGA, four Ethernet PHYs, RAM and Flash. The NIOS II softcore CPU (with MMU) provides basic functions such as initialization of the device and sending supervision.

The documentation includes a quickstart guide and a detailed manual. The quickstart guide describes the reference implementation, how to rebuild it and how to run the testbench. The manual describes the Core interfaces, the process of porting to a new platform, the purpose and working of internal modules, the register set and most of the internal signals.


The ZHAW HSR Core provides a byte-oriented signal interface to connect to 100 Mbit/s full-duplex Ethernet. To connect to a standard PHY, a conversion to MII is provided. To connect to the CPU for supervision, management, and link-local protocols, a Wishbone interface is provided. 

The IP Core implements the switching rules according to IEC 62439-3 section 5 and supports cut-through switching for low latency on the ring ports. The reference implementation is shown below.

Configuration Variant

The IP Core can be configured to use FPGA-Internal RAM. It is also possible to use an external CPU connected via Ethernet. However the CPU still needs access to the registers of the IP Core.

HSR Redbox

InES bietet für Labor und Testzwecke eine HSR-RedBox an: LAN A und B für die Ringanschaltung und LAN I (Interlink) für nicht-HSR-fähige Knoten.